SPDT 2018
Nov 1-2
Phoenix Convention Center
Arizona, USA
in conjunction with ITC and ISTFA
ABOUT
IEEE International Workshop on Silicon Photonics Design and Test (SPDT) focuses exclusively on design and test of silicon photonics systems, including design, EDA tools, manufacturing, as well as architectures and co-design methods to integrate silicon photonics into traditional electronics systems. In the emerging data center, cloud computing and high performance computer eras, silicon photonics is a key enabler. SPDT offers a forum to collaborate the silicon photonics experts with electrical design and test researchers and practitioners to present and discuss these challenges and emerging solutions.
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SPDT2018 will be held in conjunction with ITC2018 and ISTFA2018.
To find out more:
Committee
Committee
Organization Committee
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General Chair
Yinchieh Lai – NCTU
Vice General Chair
Chen-Huan Chiang – Intel
Program Chair
Jyehong (Jason) Chen – NCTU
Finance Chair
Lindor Henrickson – NCHU
Panel
TBD
Publications
You-Chia Chang – NCTU
Publicity
Vijit Bedi – US Air Force Lab
Registration
TBD
Audio/Visual
March Chen – ITRI
Program Committee
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Jiang Xu – HKUST
TBD
Steering Committee
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Jyehong (Jason) Chen – NCTU
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March Chen – ITRI
Chen-Huan Chiang – Intel
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Lindor Henrickson – NCHU
Yinchieh Lai – NCTU
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Tentative Schedule
(Subject to Change)
Nov 1
14:00-19:00
Registeration
Nov 2
07:00-08:00
Breakfast
16:00-17:00
Welcome Message
Opening Keynote
07:30-10:00
Registeration
17:00-18:30
Technical Session #1
08:00-10:00
Technical Session #2
18:30-20:30
Reception
10:00-10:30
Coffee Break
10:30-12:00
Technical Session #3
12:00-13:00
Lunch
13:00-14:30
Technical Session #4
14:30-15:00
Break
15:00-16:00
Panel
Paper Submission
IEEE Paper Template
Paper Submission
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Full Paper submissions (of up to six pages) are preferred, but Extended Abstract submissions (of at least two pages) are also accepted.
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Each submission must be in a standard IEEE format.
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Submissions should be made electronically as a single PDF file by clicking the above icon.
Contact Organizer
3600 Juliette Lane, Santa Clara, CA 95054
chen-huan.chiang@intel.com | Tel: 408-765-4038